Breakthrough Bandwidth
SerDes Hits New Heights

A little over a year ago, when we wrote our last feature on high-speed serial I/O, you might have felt safe. You could read the article with a secure fascination, isolated from personal involvement with the risks of the technology and amused at the lengths to which those telecom types would go in order to cram more bandwidth onto the backplane - safe in the knowledge that your own precisely-tuned parallel busses were merrily megabitting away on your little low-tech circuit boards. Now, the subject may feel a bit more uncomfortable. With standards like PCI Express gaining increasing momentum, your inevitable day of doom looms large. It won't be long before you'll have to walk over to your technical bookshelf (the dusty end) and pick up that college analog textbook that you've schlepped along with you through your last four jobs without cracking the cover. It's the one that you didn't return to the bookstore for credit because you hoped that its presence in your bookcase would camouflage the fact that your digitally-biased brain remembered absolutely nothing from any of those classes.

Try to remain calm. The industry feels your fear.

"Designer education is the biggest barrier to SerDes adoption today," says Abhijit Athavale, Serial Connectivity Marketing Manager at Xilinx. "At first, it was just the top-tier telecom customers that were interested in SerDes. They were comfortable with the analog design component, the signal integrity issues, and the idea of bit-error-rates. Mainstream designers are more suspicious of any situation where errors are assumed." [more]

Making the Jump to 10G
by Abhijit Athavale and Brian Seemann, Xilinx, Inc.

There is a radical shift in the beliefs about high speed serial feasibility as it moves beyond 3 Gbps on up to 10 Gbps. In a matter of few short years, the industry has gone from saying "impossible" to the concept of 10 Gbps with existing CMOS NRZ signaling to today, where all the required productized elements are in place for delivering manufacturable systems operational anywhere from 2.5 to 10Gbps. These components include: off the shelf transceivers, backplanes and connectors.  The reason for this shift has been a concerted, partnered effort by all parties including semiconductor vendors, backplane, connector manufacturers and signal integrity experts. Moving beyond 3 Gbps was not going to happen just by having super connectors or ultra high speed silicon or exotic materials. A strong coalition between all the players mentioned above has moved the entire industry forward.

Xilinx has not only found itself in the middle of this transition, but also played an integral role in it. Central to emergence of key technologies such as high speed transceivers, standardized backplanes and connectors has been the availability of advanced, high performance 2.5 to 10Gbps transceivers integrated into a highly digital, programmable environment such as the Xilinx Virtex™-II Pro X/ Virtex-4 FPGAs. With the wide availability of such devices, high speed serial is now available to every digital designer building systems today. FPGAs with serial I/O have created a tipping point for serial I/O. No longer is high speed serial the domain of a few who could afford to develop custom chips, backplanes and connectors in order to achieve their performance targets. [more]

Co-Verification Methodology for Platform FPGAs
by Milan Saini, Xilinx, Inc.
and Ross Nelson, Mentor Graphics

The emergence of affordable high-end FPGAs is making them the technology of choice for an increasing number of electronics products that previously were the exclusive domain of ASICs. Offering unprecedented levels of integration on a single chip, today’s programmable devices have widely expanded the size, scope, and range of applications that can now be deployed on them .

To ensure a fast and efficient implementation of these advanced, feature rich FPGAs, designers need access to the latest in productivity enhancing electronic design automation (EDA) tools and methodologies. For years, hardware/software (HW/SW) co-verification has been commonly used to debug ASIC SoC designs. Now, with embedded processors such as the PowerPC405 from IBM, combined with multi-million gate capacities commonplace in Virtex series FPGAs, there is an increased relevance for ASIC-strength methodologies such as co-verification to add value in the FPGA design space.

The Debug Challenge
By various accounts, design verification is the most serious bottleneck that engineers face in delivering multi-million gate SoCs. In the case of ASICs, it is not uncommon for verification teams to spend as much as 50 to 70 percent of their time in verification and debug. In FPGAs, where the penalty of a design error is not as severe and a design respin is a matter of hours not months, there is, nonetheless, still an obvious need to introduce efficient debug methodologies that enable design teams to identify and fix errors early on in the process. [more]